[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Jacob Lifshay]

On Mon, May 6, 2019 at 4:06 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>  that's the entire power budget of the entire design blown solely and
> exclusively on the DRAM.
I was expecting the power budget of 2.5W to be just for the SoC, not
the RAM as well. I wouldn't expect the FPGA-based solution to be that
low power anyway, since FPGAs are less efficient than ASICs. I'd
expect it to be less than 10W for the FPGAs and a watt or so for the
memory.

>  by sticking to the lower speeds, we avoid the data corruption by
> simply not pushing the ICs beyond the point where a Chinese ODM cannot
> do the layout and the task has to be allocated to a Taiwan or Western
> subcontractor, who will charge a minimum of USD $50k.
Note that there are plenty of capable Chinese contractors that can do
high-frequency PCB design (not that they will be cheaper).

>  a reasonably-above-average Chinese ODM can easily handle the DRAM
> layout for only 800mhz DDR3/LPDDR3, would cost only around the USD
> $10k mark, and stand a high probability of success, pass EMI / RF
> regulations, and not have any data corruption.
>
>  ECC is really for servers pushing the limits.  i appreciate that we,
> as engineers, think in terms of wanting the reliability. it just... it
> has a price.
If the memory bus has a few extra data lines, that's close to all that
needs to be added to the PCB to support ECC (assuming the memory
itself does anyway). I wasn't expecting the final SoC to require ECC,
but if we designed it so we could convert a few extra GPIO pins to
additional bits for the memory bus, it should have a quite low
incremental cost.


Jacob