[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Luke Kenneth Casson Leighton]

On Mon, May 6, 2019 at 10:46 PM Hendrik Boom <hendrik at topoi.pooq.com> wrote:
>
> On Mon, May 06, 2019 at 10:40:55AM -0700, Jacob Lifshay wrote:
> > I think one thing that would probably be quite useful is, instead of having
> > ddr3 ram directly on the board, to have a ddr3 dimm or sodimm socket so
> > that the user can upgrade the ram to as much as they're willing to buy and
> > will fit, or just not use any if they don't need any. I think we should
> > support 64-bit sodimms (no support for ECC) and if we want to emulate
> > smaller bus widths, we can just disconnect some of the data lines.
>
> I would very much like to have support for detecting memory corruption,
> even if many users will leave it turned off.  For my purposes
> (preventing data corruption) a hard stop would suffice; other users
> would prefer something more flexible, such as an exception to the OS.
>
> I don't need correction.  I need corruption to be detected.  I'd prefer
> no data to wrong data.
>
> But I've lived without this for many years now; I suppose I could go
> on doing that.  But something in this direction is gradually getting
> important as memories and data stores get bigger and bigger.

 the initial goal is a mobile-class low-power design.  that means
keeping the memory usage down to around the 400mhz clock rate (LPDDR3
800mhz), which, for a 32-bit data bus, means that the DRAM IC itself
needs around 300mW (0.3mW) of power.

 as that clock rate doubles (to do e.g. HDMI2) the power requirement
goes up FOUR times.  1600mhz DDR3 (an 800mhz clock rate) now needs 1.2
*watts*.

 except, HDMI2 is so data-hungry, not even one 1600mhz DDR3 RAM IC can
cope, so you need two.

 that's the entire power budget of the entire design blown solely and
exclusively on the DRAM.

 by sticking to the lower speeds, we avoid the data corruption by
simply not pushing the ICs beyond the point where a Chinese ODM cannot
do the layout and the task has to be allocated to a Taiwan or Western
subcontractor, who will charge a minimum of USD $50k.

 a reasonably-above-average Chinese ODM can easily handle the DRAM
layout for only 800mhz DDR3/LPDDR3, would cost only around the USD
$10k mark, and stand a high probability of success, pass EMI / RF
regulations, and not have any data corruption.

 ECC is really for servers pushing the limits.  i appreciate that we,
as engineers, think in terms of wanting the reliability. it just... it
has a price.

l.