[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Luke Kenneth Casson Leighton]

On Tue, May 7, 2019 at 12:31 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> Ok, though I'd expect two SODIMM (not DIMM) sockets to fit in less
> than the area of a credit card.

 not and fit anything else on the same side of the PCB as well:
 https://www.crowdsupply.com/img/ec40/eoma-cardfront_png_content-body-gallery.jpg

 this is the EOMA68-A20 Computer Card that i designed.   it's a 43 x
78mm PCB, to fit inside PCMCIA casework, which is *exactly* the same
size - literally - as 5 credit cards :)

 an SODIMM on that would mean no room for power IC circuitry (1/4 of
the PCB, in the top left corner), no room for the SoC (even though
it's only 18x18mm), etc. etc.

 also... heat dissipation becomes a serious problem, and thermal
design considerations have to be taken into account.  a 2.5 watt SoC,
a ceramic case is sufficient, and the heat that goes through the BGA
balls is not so large that the PCB that small can't dissipate it.


> >  also, the ECP5 only supports up to 800mhz DDR (a 400mhz clock rate).
> > actually finding SODIMMs that are *guaranteed* to go down to that rate
> > is likely to be challenging.
> Ok. In my experience, underclocking memory seems to work fine (not
> that I have much experience with 400Mhz DDR3 memory).

 DDR3 x8 RAM ICs are now a special-order item.  DDR3 x16 are still
obtainable.  LPDDR3 is still used hugely, mostly in smartphones, hence
why i recommend it over DDR3 / DDR3L.

> I never suggested that we should have both SODIMMS connected to one
> ECP5, I had suggested two SODIMM connected to two separate ECP5s, 1:1.

 oh ok :)  the PCB size required would be somewhere around... a 5in x
5in design, possibly 4in x 5in.  definitely not credit-card-sized.

> >  * not strictly necessary given the initial target (embedded mobile).
> > 720p30 is really modest (a reason why it was chosen) - only 3 million
> > pixels / sec - which does not put too great a strain on the (shared)
> > memory bus bandwidth.
> >
> >  * over the target power budget (2.5W)
> I had suggested that we could use a narrower memory bus (eg 32 or 36
> bits instead of 64 or 72 bits) to simulate using a smaller number of
> ram chips.

 sorry, didn't spot that.  the downside of an SODIMM is: the data bus
width is fixed, and you can't work around that.  if you do (reduce the
bus width to 32 bits), the only way to do so is to ignore *HALF* the
SODIMM's data capacity.

 so, if the SODIMM is 64-bit data bus, you absolutely *must* support a
64-bit data bus.  which is another one of the reasons why i don't like
using them in embedded designs.

 aside from the space issues.

 embedded is a totally different world from the majority of computer
users' experience.

> > > Lattice document for connecting ddr3 dram to ecp5:
> > > http://www.latticesemi.com/view_document?document_id=50467
> The above document specifically states that a single ECP5 supports a
> 72-bit memory bus (search for "sodimm").

 oo that's worth knowing.  i hadn't been able to find that.

l.