[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Jacob Lifshay]

On Mon, May 6, 2019 at 3:58 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Mon, May 6, 2019 at 6:41 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > I think one thing that would probably be quite useful is, instead of having
> > ddr3 ram directly on the board, to have a ddr3 dimm or sodimm socket so
> > that the user can upgrade the ram to as much as they're willing to buy and
> > will fit, or just not use any if they don't need any. I think we should
> > support 64-bit sodimms (no support for ECC) and if we want to emulate
> > smaller bus widths, we can just disconnect some of the data lines.
>
>  ah, i forgot to mention: the potential sponsor is used to doing
> credit-card-sized computers.  SODIMM sockets are a different ballgame
> that they may not be used to (in both form-factor as well as
> engineering expertise).
Ok, though I'd expect two SODIMM (not DIMM) sockets to fit in less
than the area of a credit card.

>  also, the ECP5 only supports up to 800mhz DDR (a 400mhz clock rate).
> actually finding SODIMMs that are *guaranteed* to go down to that rate
> is likely to be challenging.
Ok. In my experience, underclocking memory seems to work fine (not
that I have much experience with 400Mhz DDR3 memory).

>  a BGA-soldered LPDDR3 RAM IC makes it the chinese manufacturer's
> problem to source the correct IC, and guarantees to the end-user that
> it'll work.
>
>  also, 64-bit SODIMMs basically means twin 80-pin interfaces for each
> 32-bit data bus width.  yes, really, DDR3 needs a staggering 80 pins,
> for control, clock, negotiation and so on.  yes it's possible to share
> the address lines, however not much else.  it'd mean around 140-150
> pins dedicated to 64-bit-wide signal paths.
>
>  now, i'm not sure if a single ECP5 can even cope with that (handle
> two DDR3 data buses simultaneously).
I never suggested that we should have both SODIMMS connected to one
ECP5, I had suggested two SODIMM connected to two separate ECP5s, 1:1.

>  * not strictly necessary given the initial target (embedded mobile).
> 720p30 is really modest (a reason why it was chosen) - only 3 million
> pixels / sec - which does not put too great a strain on the (shared)
> memory bus bandwidth.
>
>  * over the target power budget (2.5W)
I had suggested that we could use a narrower memory bus (eg 32 or 36
bits instead of 64 or 72 bits) to simulate using a smaller number of
ram chips.

> > Lattice document for connecting ddr3 dram to ecp5:
> > http://www.latticesemi.com/view_document?document_id=50467
The above document specifically states that a single ECP5 supports a
72-bit memory bus (search for "sodimm").

Jacob