[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Luke Kenneth Casson Leighton]

On Mon, May 6, 2019 at 6:41 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> I think one thing that would probably be quite useful is, instead of having
> ddr3 ram directly on the board, to have a ddr3 dimm or sodimm socket so
> that the user can upgrade the ram to as much as they're willing to buy and
> will fit, or just not use any if they don't need any. I think we should
> support 64-bit sodimms (no support for ECC) and if we want to emulate
> smaller bus widths, we can just disconnect some of the data lines.

 ah, i forgot to mention: the potential sponsor is used to doing
credit-card-sized computers.  SODIMM sockets are a different ballgame
that they may not be used to (in both form-factor as well as
engineering expertise).

 also, the ECP5 only supports up to 800mhz DDR (a 400mhz clock rate).
actually finding SODIMMs that are *guaranteed* to go down to that rate
is likely to be challenging.

and, if it doesn't work, will result in end-user complaints.

 a BGA-soldered LPDDR3 RAM IC makes it the chinese manufacturer's
problem to source the correct IC, and guarantees to the end-user that
it'll work.

 also, 64-bit SODIMMs basically means twin 80-pin interfaces for each
32-bit data bus width.  yes, really, DDR3 needs a staggering 80 pins,
for control, clock, negotiation and so on.  yes it's possible to share
the address lines, however not much else.  it'd mean around 140-150
pins dedicated to 64-bit-wide signal paths.

 now, i'm not sure if a single ECP5 can even cope with that (handle
two DDR3 data buses simultaneously).

 even if it did... the amount of data is:

 * well beyond what 8x 300mhz HyperRAM interfaces can handle (double).
8x 300mhz = 2400mbytes/sec, where 800mhz DDR3/LPDDR3 @ 32-bit
generates 3200 mbytes/sec.  twin 800mhz interfaces would be 6400
mbytes/sec.

  we would need 16x HyperRAM interfaces to cope, basically.  that's
208 pins.  (1x HyperRAM interface needs 13 pins)

 * not strictly necessary given the initial target (embedded mobile).
720p30 is really modest (a reason why it was chosen) - only 3 million
pixels / sec - which does not put too great a strain on the (shared)
memory bus bandwidth.

 * over the target power budget (2.5W)

> Lattice document for connecting ddr3 dram to ecp5:
> http://www.latticesemi.com/view_document?document_id=50467

 yes i found this last week, good reminder.  one of the "setup" pages
using the lattice config tool does actually have twin 32-bit buses
(and the usual 14-or-so DDR3 address pins)... i don't know if that's
hi/lo (DDR-rising, DDR-falling) or whether it's *actual* 64-bit.

 i honestly can't tell, from this, either:
 https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py

 worst case we'd need one ECP5 per LPDDR3 IC... then to have the
HyperRAM Buses do Chip-Select (CS#0, CS#1) and route all 8 HyperRAM
Buses to both ECP5s.

l.