[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Hendrik Boom]

On Mon, May 06, 2019 at 10:40:55AM -0700, Jacob Lifshay wrote:
> I think one thing that would probably be quite useful is, instead of having
> ddr3 ram directly on the board, to have a ddr3 dimm or sodimm socket so
> that the user can upgrade the ram to as much as they're willing to buy and
> will fit, or just not use any if they don't need any. I think we should
> support 64-bit sodimms (no support for ECC) and if we want to emulate
> smaller bus widths, we can just disconnect some of the data lines.

I would very much like to have support for detecting memory corruption, 
even if many users will leave it turned off.  For my purposes 
(preventing data corruption) a hard stop would suffice; other users 
would prefer something more flexible, such as an exception to the OS.

I don't need correction.  I need corruption to be detected.  I'd prefer 
no data to wrong data.

But I've lived without this for many years now; I suppose I could go 
on doing that.  But something in this direction is gradually getting 
important as memories and data stores get bigger and bigger.

I'd accept that it may be outside th scope of the project.

-- hendrik

> 
> I think it might be a good idea to have 2 sockets, each attached to a
> separate ecp5, to facilitate testing NUMA systems (for the libre-riscv SoC,
> that would be two SoCs connected together using OmniXtend or similar). We
> can't share a socket between fpgas because the address and control lines
> are common to all chips on a dimm.
> 
> After a cursory search, I found the socket for around $3, so we shouldn't
> have to worry about cost too much.
> 
> Lattice document for connecting ddr3 dram to ecp5:
> http://www.latticesemi.com/view_document?document_id=50467
> 
> Jacob
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