[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Jacob Lifshay]

On Mon, May 6, 2019 at 2:46 PM Hendrik Boom <hendrik at topoi.pooq.com> wrote:
>
> On Mon, May 06, 2019 at 10:40:55AM -0700, Jacob Lifshay wrote:
> > I think one thing that would probably be quite useful is, instead of having
> > ddr3 ram directly on the board, to have a ddr3 dimm or sodimm socket so
> > that the user can upgrade the ram to as much as they're willing to buy and
> > will fit, or just not use any if they don't need any. I think we should
> > support 64-bit sodimms (no support for ECC) and if we want to emulate
> > smaller bus widths, we can just disconnect some of the data lines.
>
> I would very much like to have support for detecting memory corruption,
> even if many users will leave it turned off.  For my purposes
> (preventing data corruption) a hard stop would suffice; other users
> would prefer something more flexible, such as an exception to the OS.
>
> I don't need correction.  I need corruption to be detected.  I'd prefer
> no data to wrong data.
In my opinion, we should either support correction or not bother at
all, since the extra memory hardware to support detection is only
slightly less expensive than supporting correction. I had selected
non-ECC simply because that's the easiest to obtain sodimm type and
because that means we don't have to dedicate as many pins to the
memory bus in the final SoC, since pin count is a large factor in
package cost. If we can, it would be nice to support both ECC and
non-ECC memory, rather than requiring one or the other type.

Note that on read-only caches (like the instruction cache), error
detection is sufficient since the error can be corrected by just
reloading that cache line from RAM. RW caches will need some kind of
error correction.

Jacob