[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Luke Kenneth Casson Leighton]

On Fri, Mar 29, 2019 at 3:24 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> now, i *think* i may be able to do some "automated" (dynamic,
> introspective) pipeline stages, hidden behind the scenes. i need to
> think about this a lot.

turns out to be a lot simpler than i was expecting:

 https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/pipeline_example.py;h=e612bb0c0df05fab124a870b5015431b51377d9e;hb=HEAD#l112

and that works extremely well, it automatically prepends the name of
the stage to the variables, and when one stage is linked to the
previous one it passes its "created" variables (temporarily stuffed
into a dictionary labelled __nextstage__) to the next one.

with that in place, as each stage is added, i *should* be able to
auto-construct the input spec and output spec for a
Buffered/Unbuffered pipeline... because those variables *are* the
inputs and outputs connecting the stages.

also, you can see how similar the example is to a FSM object: it
should be possible to do an "FSM" mode as *well*... all using
*exactly* the same code!

l.