[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Mar 29 15:24:26 GMT 2019


On Fri, Mar 29, 2019 at 2:51 PM Aleksandar Kostovic
<alexandar.kostovic at gmail.com> wrote:
>
> thanks for showing the concern about the readability of the actual code.
>
> > i appreciate that hypothetically, all of the code that's not related
> > to fadd, fmul, fdiv etc. could be moved to a separate python module,
> > which would greatly reduce the amount of code seen in each of fadd,
> > fmul etc. because the normalisation, packing, etc., that's all exactly
> > the same.
> > this would leave the specialcases and the actual work (mul/div/add) in
> > the module, making it more obvious what's going on...
>
> Thats exactly what i had in mind. General stuff done in the separate
> modules and operation specific cases done in fmul, fdiv.....

 i've just completed the split / move, there's now fpcommon and fpadd
- it was time to do that (previously it was not).  this is what's in
fpcommon:

corrections.py    postcalc.py       putz.py
denorm.py       normtopack.py  postnormalise.py
getop.py        pack.py        prenormalise.py   roundz.py

and fpadd contains:

add0.py  addstages.py     statemachine.py
add1.py  align.py      pipeline.py  specialcases.py

> Hopefuly you can work it out since i cant help with the current form :)

i'm actually unhappy with the code even beyond a split into separate
python modules: take fpadd/pipeline.py FPADDBase class for example:
yes, great, it shows clearly, you do special-cases plus normalisation
as the first pipeline stage, followed by align and the actual add as
the second stage, then normalisation and rounding as the third...

... however you can't actually see everything sequentially, on a
single page, and that's really annoying.

by contrast, i dug into the git history and found the old version of
nmigen_add_experiment.py, and it's actually readable.  yes, i'd split
out the denormalisation, packing etc. into functions... however the
*actual* adding bit is really, really clear.

now, i *think* i may be able to do some "automated" (dynamic,
introspective) pipeline stages, hidden behind the scenes. i need to
think about this a lot.

l.



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