[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Luke Kenneth Casson Leighton]

On Sat, Mar 30, 2019 at 11:58 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> and that works extremely well, it automatically prepends the name of
> the stage to the variables, and when one stage is linked to the
> previous one it passes its "created" variables (temporarily stuffed
> into a dictionary labelled __nextstage__) to the next one.

 good god, it actually worked.  this example actually does what is expected:

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/pipeline_example.py;h=0d060da31bf53379ce328b8efe8dd2ec9810b8d3;hb=HEAD#l97

it looks blindingly obvious, and yet actually what's going on behind
the scenes is that the assignments in each stage are NOT being
assigned to the object "p", they're being DIVERTED into an
auto-created "Stage" object, which is then passed to a Buffered or
Unbuffered Pipe object.

i can't believe it actually works.

it should be relatively straightforward and obvious how to do a FSM
variant of this: just drop all of the diverted assignments into an FSM
"State", behind the scenes, instead.

cooool :)

l.