[libre-riscv-dev] buffered pipeline

[Luke Kenneth Casson Leighton]

On Thu, Mar 14, 2019 at 8:07 AM Jacob Lifshay <programmerjake at gmail.com>
wrote:

> turns out I had checked the control logic and it was fine, but I forgot to
> have the data register do anything other than load the input from the
> previous stage.
>

 doh :)


>
> On Wed, Mar 13, 2019 at 2:22 AM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> wrote:
>
> > On Wed, Mar 13, 2019 at 8:45 AM Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> >
> > > On Wed, Mar 13, 2019, 01:39 Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> > > wrote:
> > > >  can you please write a unit test (which has the side-effect of
> > creating
> > > a
> > > > waveform as output) so that i can take a look?
> > > >
> > > sure, I'll do it in the morning though.
> >
> Working on the unit tests now.
>

i've written a few, now, including one that throws 10,000 values at a
single-stage and a dual-stage pipeline, with random delays at either end:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/test_buf_pipe.py;h=9c53431a3f78dfb7b0bdbc83371be12e56b253aa;hb=HEAD

someone named attie from irc #m-labs pointed me at this:
https://github.com/nakengelhardt/fpgagraphlib/blob/master/src/hmc_backed_fifo_tb.py

it's a way to pass co-routines to nmigen simulations, where each co-routine
(generator) will have access to the exact same dut (device under test), and
the clock signals are properly synchronised between each co-routine
(generator).

i'll take a look at modifying test_buf_pipe.py to separate out the read and
write aspects.  this is quite important to do when the number of inputs and
outputs increases.

imagine trying to synchronise and coordinate multiple input and output
signal setting and checking from a single function - it would quickly
become hell.

l.