[libre-riscv-dev] buffered pipeline

Jacob Lifshay programmerjake at gmail.com
Thu Mar 14 08:40:35 GMT 2019


I'm using the nmigen.back.pysim.Simulator class, which is apparently the
recommended solution for simulation. It supports executing multiple
generators simultaneously, you just have to watch out for checking values
immediately after a clock edge, it needs a slight delay before it
calculates the combinatorial values.

It's used like:

m = MyModule()
with Simulator(test_stage, vcd_file=open("test.vcd", "w"),
gtkw_file=open("test.gtkw", "w"), traces=[m.sig1, m.sig2]) as sim:
    clock_period = 1e-6
    sim.add_clock(clock_period)
    def process() -> Generator[Any, Any, None]:
        yield m.sig1.eq(1) # set m.sig1
        yield #wait for clock edge
        yield Delay(1e-7) # delay 100ns
        sig2_value = yield m.sig2 # read sig2 as an int
        print(sig2_value)
        yield # clock some more
    sim.add_sync_process(process)
    sim.run()

Jacob Lifshay

On Thu, Mar 14, 2019 at 1:29 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Mar 14, 2019 at 8:07 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > turns out I had checked the control logic and it was fine, but I forgot
> to
> > have the data register do anything other than load the input from the
> > previous stage.
> >
>
>  doh :)
>
>
> >
> > On Wed, Mar 13, 2019 at 2:22 AM Luke Kenneth Casson Leighton <
> > lkcl at lkcl.net>
> > wrote:
> >
> > > On Wed, Mar 13, 2019 at 8:45 AM Jacob Lifshay <
> programmerjake at gmail.com>
> > > wrote:
> > >
> > > > On Wed, Mar 13, 2019, 01:39 Luke Kenneth Casson Leighton <
> > lkcl at lkcl.net>
> > > > wrote:
> > > > >  can you please write a unit test (which has the side-effect of
> > > creating
> > > > a
> > > > > waveform as output) so that i can take a look?
> > > > >
> > > > sure, I'll do it in the morning though.
> > >
> > Working on the unit tests now.
> >
>
> i've written a few, now, including one that throws 10,000 values at a
> single-stage and a dual-stage pipeline, with random delays at either end:
>
> https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/test_buf_pipe.py;h=9c53431a3f78dfb7b0bdbc83371be12e56b253aa;hb=HEAD
>
> someone named attie from irc #m-labs pointed me at this:
>
> https://github.com/nakengelhardt/fpgagraphlib/blob/master/src/hmc_backed_fifo_tb.py
>
> it's a way to pass co-routines to nmigen simulations, where each co-routine
> (generator) will have access to the exact same dut (device under test), and
> the clock signals are properly synchronised between each co-routine
> (generator).
>
> i'll take a look at modifying test_buf_pipe.py to separate out the read and
> write aspects.  this is quite important to do when the number of inputs and
> outputs increases.
>
> imagine trying to synchronise and coordinate multiple input and output
> signal setting and checking from a single function - it would quickly
> become hell.
>
> l.
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