[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

turns out I had checked the control logic and it was fine, but I forgot to
have the data register do anything other than load the input from the
previous stage.

On Wed, Mar 13, 2019 at 2:22 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Mar 13, 2019 at 8:45 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > On Wed, Mar 13, 2019, 01:39 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> > >  can you please write a unit test (which has the side-effect of
> creating
> > a
> > > waveform as output) so that i can take a look?
> > >
> > sure, I'll do it in the morning though.
>
Working on the unit tests now.