[libre-riscv-dev] TLB key for CAM

[Luke Kenneth Casson Leighton]

On Tue, Mar 12, 2019 at 2:39 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:

> I have gotten the CAM working as well as I want to with both a one
> cycle read and write. All operations verified through the unit test as
> well which is cool. More tests in the future but for now I think it is
> okay.

 yes, there's a couple of levels of testing: "get it working" level,
and "we're sure it works 100%" level.

 btw there's a nmigen class called "Memory" for which you'll find
there are examples:
 https://github.com/m-labs/nmigen/blob/master/examples/mem.py

 the example is of a RegisterFile.  i mention it because you created a
class called RegisterFile and it uses an Array rather than a Memory
class.

 the reason for using the Memory class is because the Memory class is
specifically designed to map down to verilog arrays / array indices,
which in turn are fully and properly recognised by synthesis tools to
map to SRAMs and ported memory, both on ASIC tools as well as FPGA
synthesis tools.

 note that for the vector engine we will need *byte* level
write-enable lines.  we will *not* be doing a 32-bit-wide read,
modify-single-byte, 32-bit-wide write cycle, we will be doing a SINGLE
cycle byte-level write.

yes this means that for 64-bit registers, 8 byte-write-enable lines
need to be activated simultaneously.

l.