[libre-riscv-dev] TLB key for CAM

[Daniel Benusovich]

>  the example is of a RegisterFile.  i mention it because you created a
> class called RegisterFile and it uses an Array rather than a Memory
> class.

Woops

>  the reason for using the Memory class is because the Memory class is
> specifically designed to map down to verilog arrays / array indices,
> which in turn are fully and properly recognised by synthesis tools to
> map to SRAMs and ported memory, both on ASIC tools as well as FPGA
> synthesis tools.

Makes sense to me. I will delete my existing RegisterFile and use a
memory block instead. Should I use the RegisterFile from the example?
It seems so nice.