[libre-riscv-dev] TLB key for CAM

[Jacob Lifshay]

On Mon, Mar 11, 2019, 19:40 Daniel Benusovich <flyingmonkeys1996 at gmail.com>
wrote:

> I have gotten the CAM working as well as I want to with both a one
> cycle read and write. All operations verified through the unit test as
> well which is cool. More tests in the future but for now I think it is
> okay.
>
> From what I understand key of the CAM in the TLB should be the VMA.
> However, this may cause collisions as multiple processes use the same
> address for many things. Should the policy be to simple replace the
> colliding entry? For instance process 1 caches VMA 0x01. Then process
> 2 get control and looks for VMA 0x01. It will have a hit in the CAM,
> but, the ASID will be incorrect and we will replace that entry. At
> least that is what makes sense to me. Otherwise we may end up with
> multiple entries in the CAM for the same key which would be bad!
>
> I was also toying with the idea of using the VMA + ASID as the key and
> never have any collisions. But I believe that destroys the idea of
> global mappings so probably not haha.
>
I think the CAM should just have the circuitry to match the VMA + ASID
combination correctly since it's not much more complex:
for entry in cam_entries.in_unspecified_order() {
    if entry.vma == vma && (entry.global || entry.asid == asid) {
        return entry;
    }
}

Jacob Lifshay