[libre-riscv-dev] Wish to work on

[Luke Kenneth Casson Leighton]

On Friday, March 8, 2019, Rishabh Jain <rishucoding at gmail.com> wrote:

> "yosys > read_verilog Cam.v" runs fine, console log ends with
> "Successfully
> finished Verilog frontend".


Great.


>
> I get a error message when I do "yosys > show" :
>
> "2. Generating Graphviz representation of design.
>
> ERROR: For formats different than 'ps' or 'dot' only one module must be
> selected.
> "


Aah I have been hand editing the verilog file and cutting it back to
contain only one module. Search "module top"


>
> But, "yosys > show -format dot " this works fine: ends with "Dumping
> module
> anonymous to page 8"


Ah great, I will try that


>
>
>
> Then, linking the python3.6 binary with python3 works. Now, python3
> invokes
> python3.6 binary. Thanks!
>
>
Cool.


>
>
> I was able to observe the waveform.
>
> I tried to right click on "top" (position is left top side in my case),


>
Yes. Same here


>  but
> not option were coming.


Hm, left click first? Signals should appear in lower part of left pane.



> Though, I was able to load all the signals by "Search -> Signal Search
> Hierarchy
> -> select 'top' and insert"
>
>
>
> Yes, the waveforms are pretty clean and clear.
>
>
>
> Yep, I have cocotb installed.
>
> Now, i guess the tools are working fine.
> can you share the specifications for TLB and CAM which we intend to
> develop?
>
>
Still being discussed, search archives for subjects "TLB".

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/

We really need to start using bugtracker soon, number of outstanding issues
and discussions is beyond ability to memorise.

L.



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