[libre-riscv-dev] Wish to work on

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, Mar 8, 2019 at 4:32 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
>
>
> On Friday, March 8, 2019, Rishabh Jain <rishucoding at gmail.com> wrote:
>>
>> "yosys > read_verilog Cam.v" runs fine, console log ends with
>> "Successfully
>> finished Verilog frontend".
>
>
> Great.
>
>>
>>
>> I get a error message when I do "yosys > show" :
>>
>> "2. Generating Graphviz representation of design.
>>
>> ERROR: For formats different than 'ps' or 'dot' only one module must be
>> selected.
>> "
>
>
> Aah I have been hand editing the verilog file and cutting it back to contain only one module. Search "module top"
>
>>
>>
>> But, "yosys > show -format dot " this works fine: ends with "Dumping
>> module
>> anonymous to page 8"
>
>
> Ah great, I will try that

cool, yes, it worked: i couldn't get xdot to show different pages,
however the actual generation worked, and i got an error "unexpected
digraph" or something, from xdot.

better to cut out all but the one module from the verilog file.

l.