[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

aleksander, got an idea.  can you turn that zipcpu example into an
actual working simple pipeline example (logic = "add 1 to number"),
chain two of them together, *in verilog*, and write a unit test *in
verilog* as well?

then and only then once the verilog unit test passes we convert it to nmigen?

i will work from the other end, replacing "ack" with "busy" in the
add.py, we will meet somewhere in the middle.

that way you work from a known position of strength in an incremental
fashion and so do i.

l.