[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Tue, Feb 26, 2019 at 8:12 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> aleksander, got an idea.  can you turn that zipcpu example into an
> actual working simple pipeline example (logic = "add 1 to number"),
> chain two of them together, *in verilog*, and write a unit test *in
> verilog* as well?

 rrright, i managed to semi-work-out what's going on.  the "stb"
signal needed to be lowered on the inputs as soon as possible, and
that means immediately the clock-cycle after the module "acks".

 by *not* doing that, add1 was actually doing a + b *TWICE*, because
the a and b inputs were left in a state where, after the 1st add
completed, they went back to "get_a" state, saw that the STB signals
were asserted, and went "oh, we're being asked to add these 2 values
together"... so they did.

 the chaining now works, however what i do not know is, whether it is
optimal and whether it is suitable for high-performance usage.

 (hint, aleksander: we still need that zipcpu buffered pipeline investigated!)

basically the way it's supposed to work, the stb is left on to
indicate that new data is to be read *on every clock cycle* (as long
as it's not "busy" that is).  that rule was being broken by leaving
the input stbs on with *OLD* data, hence the need for further
investigation.


l.