[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Saturday, February 23, 2019, Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> To be clear, you are trying to make it so that each stage becomes its own
> "small module".


Yes.


>
>  So for example in multiply, a state get_a is a small
> module, get_b, special cases, normalizations... are supposed to be small
> modules.


Or, those that can be combined into single cycle combinatorial blocks, yes.


>
> And you are doing it to better pipeline it right?


Yes.


> Than i think this will be a good read
> https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html


Hey that's zipcpu. Cool.


> What i like the most in that is part about "The traveling CE to reduce the
> latency"
>
>
Ha, that's funny, it mentions STB and ACK, which is exactly what is on the
front and end of the code.

A is protected by stb and ack, so is B and so is z.




-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68