[libre-riscv-dev] IEEE754 FPU

[Aleksandar Kostovic]

To be clear, you are trying to make it so that each stage becomes its own
"small module". So for example in multiply, a state get_a is a small
module, get_b, special cases, normalizations... are supposed to be small
modules. And you are doing it to better pipeline it right?
Than i think this will be a good read
https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
What i like the most in that is part about "The traveling CE to reduce the
latency"

On Fri, Feb 22, 2019 at 12:20 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> Ok the refactoring, separation between input and output, isn't working.
> Each time I try to separate them, the chain is lost.
>
> Am not sure how to do this, it's complicated by some states taking the same
> input as output, and also the special cases jumping to the end state.
>
> L.
>
>
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