[libre-riscv-dev] IEEE754 FPU

[Jacob Lifshay]

refactor each stage to only read values from the immediately previous stage
then as a final step switch from a state machine to a pipeline.

On Thu, Feb 21, 2019, 00:09 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> ok i'm a little bit stuck on how to proceed in morphing the jondawson
> design to a pipeline structure in a progressive fashion that will
> allow unit tests to be run at each part of the conversion process...
> *and* preserve the ability to specify that, actually, we don't want a
> pipeline layout, we want a *state* based layout.
>
> this so that the same infrastructure could be used to create a
> pipelined div unit or a state-based div unit, or a pipelined sqrt or a
> state-based div unit, without requiring the maintenance of two
> separate codebases.
>
> basically i'm quite lost :)
>
> i'm slowly formulating a plan that each stage - normalisation, decode,
> add, denormalisation - requires input variables and output variables
> that must be separated.
>
> also i am kinda working out that we would need a variant of
> pipeline.py that was, say... called "stateline.py', and that something
> much more explicit such as having a class that explicitly declared
> inputs to one stage that needed to match with outputs to the next
> might be a better idea.
>
> thoughts appreciated.
>
> l.
>
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