[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Thu, Feb 21, 2019 at 8:13 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> refactor each stage to only read values from the immediately previous stage
> then as a final step switch from a state machine to a pipeline.

 makes sense.  so, i'm moving each stage into its own separate class,
giving them "inputs" and "outputs", let's see how that goes.

l.