[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

ok i'm a little bit stuck on how to proceed in morphing the jondawson
design to a pipeline structure in a progressive fashion that will
allow unit tests to be run at each part of the conversion process...
*and* preserve the ability to specify that, actually, we don't want a
pipeline layout, we want a *state* based layout.

this so that the same infrastructure could be used to create a
pipelined div unit or a state-based div unit, or a pipelined sqrt or a
state-based div unit, without requiring the maintenance of two
separate codebases.

basically i'm quite lost :)

i'm slowly formulating a plan that each stage - normalisation, decode,
add, denormalisation - requires input variables and output variables
that must be separated.

also i am kinda working out that we would need a variant of
pipeline.py that was, say... called "stateline.py', and that something
much more explicit such as having a class that explicitly declared
inputs to one stage that needed to match with outputs to the next
might be a better idea.

thoughts appreciated.

l.