[libre-riscv-dev] TLB CAM data format

[Luke Kenneth Casson Leighton]

On Thu, Feb 14, 2019 at 6:28 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
>
> I am planning to have the data in the CAM be formatted like so:
>
> # Item (Bits)
> # Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
>
> Tag should be at the end as it will be changing based on the associativity
> we choose. Since testing and changes are bound to occur this is the place
> for it to be.
>
> The ASID and PTE are fixed in size so they are stuck where they are forever
> more. Nice thing is we get a constant starting bit location for the tag
> data.
>
> Let me know if this makes sense. It does to me.

 reminds me: i went over the code, CAMs are key-value stores.  in
hardware, they're *parallel* comparators (which is why they're so
power-hungry, because every single read hits EVERY single one of the
CAM entries).

the nmigen Memory class is *not* a CAM, it is an SRAM.

so, basically, we need to write our own key-value store "class",
because a CAM is going to be needed in several places.  this would be
a really good simple class to do some simulations / unit tests on, and
get a feel for how that's going to work out.

l.