[libre-riscv-dev] My plans for January 2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Dec 22 17:16:26 GMT 2019
On 12/22/19, Tobias Platen <hacks2019 at platen-software.de> wrote:
> I plan to continue working on the virtual memory subsystem of the
> libre-riscv SOC in January 2020.
ok - just bear in mind that we don't know yet whether we will be using
Power Architecture VM or RISC-V VM, so there's no available budget
until we know.
i've a message outstanding to hugh from the [brief] discussion i had last month.
> The first step will be likely converting the existing modules from
> system verilog to nmigen.
this would at least be a useful way to improve sv2nmigen.
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