[libre-riscv-dev] My plans for January 2020

Tobias Platen hacks2019 at platen-software.de
Sun Dec 22 11:22:34 GMT 2019

I plan to continue working on the virtual memory subsystem of the 
libre-riscv SOC in January 2020.

The first step will be likely converting the existing modules from 
system verilog to nmigen.


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