[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

[Jacob Lifshay]

On Fri, Aug 30, 2019, 18:02 Daniel Petrisko <petrisko at cs.washington.edu>
wrote:

> > I assume here that adds are more useful than anything else except what
> is available now.
>
> Atomic adds are also significantly more expensive (gates) than other CSR
> operations. Since CSRs operations are not typically performance critical, I
> think most architects would rather reuse the ALU with a traditional read
> modify write sequence.
>
> An extra 64 bit adder for atomic CSR adds would be unacceptable for
> low-end implementations, and reusing the ALU for 3-part atomic CSR adds is
> unnecessary complexity.
>
> As suggested earlier, memory-mapping CSRs would allow one to get all AMOs
> for “free”, but in a very platform-specific way. Does anyone know if
> there’s precedent for that scheme, in current RISC-V implementations or
> uarchs for other ISAs?


If I recall correctly, x86 has the hart-local interrupt/timer unit memory
mapped.

Jacob Lifshay