[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Looking at test_multiply, it is quite hard to track things, it would appear
that the argument "register_levels" is the key.

Is it the case that if register_levels is set to contain one single value that
code to create one "stage" of a pipeline will be created?

Is it then the case that if an EXTERNAL for loop was put together, with each
iteration of that loop creating an instance of a Mul_8_16_32_64 with one and
only one "level" in each, and these "levels" were then manually connected
together, that a full pipelined Mul would be created?

If so, there is very little actual work needed to be done to get this code to
conform to the Stage API.

In addition, the graphviz diagrams would become much clearer, as each cycle
would be under its own module.

The last time I checked the graphviz it took xdot about 30 seconds @ 100% CPU
to process (a bad sign), the framerate on display was about 3 seconds per frame
(not 3 frames per second), and it was impossible to make out the gates at full
screen, there were just far too many connections and blocks.

So it has to be split up anyway.

A parameter can be added to request that sync *not* be used, with an assert to
check that len(register_levels) == 1 if that is the case.

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