[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Aug 24 20:05:10 BST 2019


--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
I managed to rework the multiplier code, will write a test tomorrow.

Whilst the ALU parts of this experiment are easy enough, control and decision
making is not. Mux can be made a class member of the partitioned signal,
however m.If and m.Case cannot.

Fortunately i think Case is never used except in things like global operands,
however m.If and Else are used all over the place.

I haven't yet fully thought through how m.If when made partitionable would even

It would need to hide a set of *adaptive* boolean tests, where the objects
within the context would also need the same partitioning.

It is actually quite fascinating.

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