[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Aug 17 05:34:09 BST 2019


--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
I renamed the FPDIV classes and the submodule, calling them FPDivPreFPAdjust
and FPDivPostToFPFormat.

Also the transparent latch idea is apparently something that has been done
before, successfully, and was quite easy to add, see issue #133.

The Pipeline / StageAPI supports FSMs, combinatorial chaining, actual pipeline
registers, now also flexible (transparent) dynamic registers, and anything else
that a *future* user of this API can envisage.

Use of sync terminates all and any possibity of the use of this extremely
flexible, straightforward API and attempting to do so requires special cases
and/or massive complications.

We do not have time for that, and it is not desirable anyway.

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