[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #5)
> 
> > whoever didn't actually write it. the multiplier is designed so that it acts
> > like a simple pipeline where every input comes out exactly N stages later,
> > where N is configured by the instantiating code.
> 
> If the code is not doing single cycle results we cannot use it.

yes we can, we just need to tell the pipeline API "this takes 3 stages instead
of one, so insert extra registers on the control signals"

> If the multiplier code has an API that is very similar to that of div_core,
> the problem is solved.
> 
> Can you do that?

Yes, but it will be invasive.

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