[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Aug 14 21:27:55 BST 2019


--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #7)
> (In reply to Jacob Lifshay from comment #5)
> .
> > 
> > Note that I did also write a partitioned adder and all partitioned bitwise
> > ops (and/or/xor/not, but not shift/rotate/anything that communicates between
> > bits) are identical to the non-partitioned ops.
> > 
> > the partitioned adder should be quite easily updated to an add/subtracter.
> Great.
> Also need comparators GE LE GT LT EQ NE. Can you do those as well?

should be easy, they should probably be implemented by adding carry-in,
carry-out, overflow-out, and is-zero-out support to PartitionedAdder and
implementing the compare ops in terms of subtract and check flags.

Note that branching on the compare result won't work (so bool() should raise an
exception) since there are multiple results.

Mux should still work if the compare ops return all ones for true and all zeros
for false, since then it's equivalent to a bitwise mux.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list