[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal

[Dan Petrisko]

>
> Also appreciate the microcode suggestions, have to give that some serious
> thought, whether to do something truly microcode-like or whether to do just
> a mini SRAM that contains subroutines that reprogrammable RISCV opcodes can
> use.


I would advise being cautiously analytical about this approach.  SRAMs
scale much more poorly than logic in advanced tech nodes, especially
low-capacity SRAMs.  It may be more area efficient to just implement the
hardware rather than microcode (not to mention performant).

Of course, programmability is beneficial for post-tapeout
enhancements/bugfixes (which also requires a loading mechanism, which is a
non-trivial addition if it's the only ucode in the design).

Best,
Dan Petrisko



On Tue, Aug 13, 2019 at 5:05 PM lkcl <luke.leighton at gmail.com> wrote:

> On Tuesday, August 13, 2019 at 11:40:39 PM UTC+8, MitchAlsup wrote:
>
> > My actual implementation folds ATAN into ATAN2 and changes the last 2
> lines into::
>
> Thx Mitch have made a note so it's not lost in list noise.
>
> Also appreciate the microcode suggestions, have to give that some serious
> thought, whether to do something truly microcode-like or whether to do just
> a mini SRAM that contains subroutines that reprogrammable RISCV opcodes can
> use.
>
> Much lower level may prove more useful, micro code operations to do FP
> prenormalisation, post normalisation etc. all at expanded bitwidths.
>
> L.
>
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