[libre-riscv-dev] implementing the TLB Replacement Policy
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Aug 13 20:56:05 BST 2019
On Wednesday, August 14, 2019, Jacob Lifshay <programmerjake at gmail.com>
> On Tue, Aug 13, 2019, 12:44 Tobias Platen <hacks2019 at platen-software.de>
> > I began working on the unit test for the still incomplete TLB.
> > When I looked into the write_l1 method I saw that only the
> > first CAM entry is updated, all others are never changed.
> > I have just started reading
> > https://www.bottomupcs.com/hardware_support_for_virtual_memory.xhtml
> > but that does not explain how to implement a TLB Replacement Policy.
> > I will have to think a few days before implementing anything.
> I would use a LFSR random number generator to randomly select a tlb entry
> to replace. I wrote one which I think is in the soc repo.
Yes it is already wired in.
Also the ariane code I think has one.
Tobias you need to fix the errors introduced in the first commit, first.
I sent a link to the relevant sections of the pric spec.
For 4 level TLB the last 10 bits of ppn must be used.
For 3 levels the last 20 bits are used.
What you did was to use the last 20 bits for level 4, something like that.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
More information about the libre-riscv-dev