[libre-riscv-dev] implementing the TLB Replacement Policy

[Jacob Lifshay]

On Tue, Aug 13, 2019, 12:44 Tobias Platen <hacks2019 at platen-software.de>
wrote:

> I began working on the unit test for the still incomplete TLB.
> When I looked into the write_l1 method I saw that only the
> first CAM entry is updated, all others are never changed.
>
> I have just started reading
> https://www.bottomupcs.com/hardware_support_for_virtual_memory.xhtml
> but that does not explain how to implement a TLB Replacement Policy.
> I will have to think a few days before implementing anything.
>

I would use a LFSR random number generator to randomly select a tlb entry
to replace. I wrote one which I think is in the soc repo.

Jacob