[libre-riscv-dev] [isa-dev] 3D Open Graphics Alliance
luke.leighton at gmail.com
Tue Aug 13 10:30:30 BST 2019
On Tuesday, August 13, 2019 at 7:46:22 AM UTC+1, lkcl wrote:
> the only thing is, fitting a third context (beyond the vector table format
> and the predicate table format) will need a redesign, or to go into the
> 192+ bit RV opcode format.
extended the VBLOCK format (to VBLOCK2). it's the 192+ bit RISC-V ISA
(for people not familiar with the VBLOCK format) note that it is *not*
necessary to load the entire block format into internal instruction
buffers: the PCVBLK CSR is designed to allow "restarting", following a
context-switch, so that a (minimal) implementation may go back and re-read
the VBLOCK context and then "restart" instructions in the middle of a block.
this type of scheme was, interestingly, discussed a couple of months back,
on isa-dev, independently.
the new VBLOCK2 extended format allows for specifying up to 8 registers to
be "swizzled", and also extends the number of Register and Predication
blocks that may be added as context, as well.
i think this should be *in addition* to having an *actual* MV.swizzle
instruction, because there will be circumstances where the overhead of a
VBLOCK context is greater than that of a single OP32.
note that due to the way that SV works, many-to-one "retargetting" is
permitted. i.e. any given register number in rs1 or rs2 or rd may be
requested to "redirect" to the EXACT SAME REGISTER, just with different
"context", such as element width, predicate or not-predicate,
predicate-with-zeroing, predicate-without-zeroing, and now "swizzle".
it's both powerful and confusing at the same time.
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