[libre-riscv-dev] [isa-dev] 3D Open Graphics Alliance
luke.leighton at gmail.com
Tue Aug 13 07:46:21 BST 2019
On Tuesday, August 13, 2019 at 5:58:34 AM UTC+1, Jacob Lifshay wrote:
> > On Monday, August 12, 2019 at 2:31:44 PM UTC+8, Jacob Lifshay wrote:
> > > So, you overestimated the number of immediate bits needed by quite a
> I was assuming a separate swizzle opcode instead of swizzle on every op.
> if we want to combine them, we can implement that using macro-op fusion.
found the (prelimilary, draft) page with some ideas under consideration:
i like the macro-op fusion concept.
the other alternative: VBLOCK context. [for readers not familiiar with
VBLOCK, the draft spec is
concept: mark a register as "if you use that register, within this current
VBLOCK, its use indicates a desire to change the behavior of the current
register tagging, in other words.
the only thing is, fitting a third context (beyond the vector table format
and the predicate table format) will need a redesign, or to go into the
192+ bit RV opcode format.
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