[libre-riscv-dev] [isa-dev] Re: FP reciprocal sqrt extension proposal

Hendrik Boom hendrik at topoi.pooq.com
Thu Aug 8 18:45:36 BST 2019

On Thu, Aug 08, 2019 at 09:53:57AM -0700, Allen Baum wrote:
> CO rdic is great for extremely low gate count implementations. But 
> for highest performance, there are likely much better ways.

It may be useful to provide both imlementations in out codebase, and 
use conditional execution to choose which to put in a particular chip 
design.  This leaves a choice between gate count and speed, which may 
be done differently for different applications.

Except, of course, that we have limited time and resources to produce 
our first working designs.

I'd suggest for now we choose one: whichever is the simplest, easiest 
to implement and has a reasonable chance of meeting out goals.

But stay modular enough that we could swap it out for another if we 
find we need to.

-- hendrik

> -Allen
> > On Aug 8, 2019, at 9:01 AM, 'MitchAlsup' via RISC-V ISA Dev <isa-dev at groups.riscv.org> wrote:
> > 
> > 
> > 
> >> On Thursday, August 8, 2019 at 1:46:39 AM UTC-5, lkcl wrote:
> >> Just a thought: should this be merged into Ztrans? A case could be nade either way.
> >> * The Libre RISCV FPDIV pipeline also computes SQRT and RSQRT
> >> * Some OTFC pipeline designs do RSQRT "for free"
> >> * However, if doing RSQRT chances are high it will be part of a design that needs EXP, LOG etc anyway.
> >> * CORDIC can do a ton of algorithms including SQRT, RSQRT, LOG, SIN etc.
> >> 
> >> Thoughts?
> >> 
> >> L.
> >> 
> > 
> > The Moto CORDIC unit took 80-cycles or more
> > The Intel CORDIC was similarly slow
> > Modern SQRT/RSQRT hardware will deliver results in 23-30 cycles. 
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