[libre-riscv-dev] [isa-dev] Re: FP reciprocal sqrt extension proposal
allen.baum at esperantotech.com
Thu Aug 8 17:53:57 BST 2019
CO rdic is great for extremely low gate count implementations. But for highest performance, there are likely much better ways.
> On Aug 8, 2019, at 9:01 AM, 'MitchAlsup' via RISC-V ISA Dev <isa-dev at groups.riscv.org> wrote:
>> On Thursday, August 8, 2019 at 1:46:39 AM UTC-5, lkcl wrote:
>> Just a thought: should this be merged into Ztrans? A case could be nade either way.
>> * The Libre RISCV FPDIV pipeline also computes SQRT and RSQRT
>> * Some OTFC pipeline designs do RSQRT "for free"
>> * However, if doing RSQRT chances are high it will be part of a design that needs EXP, LOG etc anyway.
>> * CORDIC can do a ton of algorithms including SQRT, RSQRT, LOG, SIN etc.
> CORDIC is SLOW
> The Moto CORDIC unit took 80-cycles or more
> The Intel CORDIC was similarly slow
> Modern SQRT/RSQRT hardware will deliver results in 23-30 cycles.
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