[libre-riscv-dev] [isa-dev] Re: FP reciprocal sqrt extension proposal

Allen Baum allen.baum at esperantotech.com
Thu Aug 8 17:53:57 BST 2019

CO rdic is great for extremely low gate count implementations. But for highest performance, there are likely much better ways.


> On Aug 8, 2019, at 9:01 AM, 'MitchAlsup' via RISC-V ISA Dev <isa-dev at groups.riscv.org> wrote:
>> On Thursday, August 8, 2019 at 1:46:39 AM UTC-5, lkcl wrote:
>> Just a thought: should this be merged into Ztrans? A case could be nade either way.
>> * The Libre RISCV FPDIV pipeline also computes SQRT and RSQRT
>> * Some OTFC pipeline designs do RSQRT "for free"
>> * However, if doing RSQRT chances are high it will be part of a design that needs EXP, LOG etc anyway.
>> * CORDIC can do a ton of algorithms including SQRT, RSQRT, LOG, SIN etc.
>> Thoughts?
>> L.
> The Moto CORDIC unit took 80-cycles or more
> The Intel CORDIC was similarly slow
> Modern SQRT/RSQRT hardware will deliver results in 23-30 cycles. 
> -- 
> You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+unsubscribe at groups.riscv.org.
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/13bb0fc5-dbb4-4e44-bce8-96058684042e%40groups.riscv.org.

More information about the libre-riscv-dev mailing list