[libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Aug 9 04:05:28 BST 2019
On Friday, August 9, 2019, Hendrik Boom <hendrik at topoi.pooq.com> wrote:
> On Thu, Aug 08, 2019 at 09:53:57AM -0700, Allen Baum wrote:
> > CO rdic is great for extremely low gate count implementations. But
> > for highest performance, there are likely much better ways.
> It may be useful to provide both imlementations in out codebase, and
> use conditional execution to choose which to put in a particular chip
> design. This leaves a choice between gate count and speed, which may
> be done differently for different applications.
If our design is to become a Reference Design for the upcoming 3D Open
Graphics Alliance this will be necessary.
> Except, of course, that we have limited time and resources to produce
> our first working designs.
Yyep. Only TBD with funding / assistance.
> I'd suggest for now we choose one: whichever is the simplest, easiest
> to implement and has a reasonable chance of meeting out goals.
There is a difference between doing that (very sensible) and developing an
> But stay modular enough that we could swap it out for another if we
> find we need to.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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