[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
grep "def p_" parse_sv.py | wc
   1095    2190   31280

*shocked*!!  that's one mmmmaaaaasive number of parser states!

luckily it is not necessary to do all of them.  UDP can be entirely
skipped, for example.  also, many of them will be incredibly
simple: "return one of the things that came through from a previous
state".

i've done a couple of the states, to see what they look like.
this is "lpvalue '=' expression ';':

expr = Node(syms.expr_stmt, [p[1], Leaf(token.EQUAL, p[2]), p[3] ])
p[0] = expr

p[2] needed doing (the lpvalue), p[3] likewise, and it comes out like this:

Node(expr_stmt, [Leaf(1, 'port1_accept_SN'), Leaf(22, '='),
                 Leaf(2, "1:'b0")])')

which when instead of doing repr, the lib2to3 "Node" class *already*
has the capability to print out the python code:

'port1_accept_SN=1:'b0'

which is, apart from the spaces, and that i haven't completed the
number-system, is exactly what's needed.


so the AST gets recursively constructed, from the leaf-nodes down,
end-result, python code!

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