[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[Hendrik Boom]

On Thu, Apr 25, 2019 at 02:00:11PM +0000, bugzilla-daemon at libre-riscv.org wrote:
> http://bugs.libre-riscv.org/show_bug.cgi?id=72
> 
> --- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> grep "def p_" parse_sv.py | wc
>    1095    2190   31280
> 
> *shocked*!!  that's one mmmmaaaaasive number of parser states!

It makes me suspect that either the language isn't well-designed,
or that the grammar formalism isn't a good match for the language.

-- hendrik