[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=sv2nmigen.git;a=summary

that's where it's at, so far.  the code's an absolute dog's dinner-looking
mess, however, incredibly, it actually walked one of axi_rab.sv's files

i've had to comment out much of the lexer for a first iteration, just to
get it up and running, rapidly.  some of that will have consequences
such as disabling the lexer's ability to detect types and imports,
which can be reintroduced incrementally.

also the timestamp recognition isn't working yet, plus the number
formats need some regex's / conversion (c code from the lexer replaced
with python that does the same job) etc. etc.

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