[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #6)

> If we have to write the systemverilog parser ourselves, I think it would be
> less work to just manually translate the systemverilog code if we have less
> than 10kloc or so of code to translate.

i'm starting to get RSI again, so "less typing" is a high priority.

ariane's 16,000 lines, axi_rab is 6,000 - both include some valuable
worked examples of axi4.  it easily takes me... a day to do 300-400
lines of verilog / sv manual translation...

we still have the jon dawson IEEE754 code to do (FCVT from 32-64 and 64-32)...

as a subproject, just for those alone it's easily justifiable on the
time it would save.

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