[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
we might be able to use slang: https://github.com/MikePopoloski/slang
there is a godbolt-style website for trying it out: http://sv-lang.com

If we have to write the systemverilog parser ourselves, I think it would be
less work to just manually translate the systemverilog code if we have less
than 10kloc or so of code to translate.

-- 
You are receiving this mail because:
You are on the CC list for the bug.