[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hm good point, let's see...

yosys> read_verilog -sv fsm_expand.sv 
1. Executing Verilog-2005 frontend.
Parsing SystemVerilog input from `fsm_expand.sv' to AST representation.
fsm_expand.sv:59: ERROR: syntax error, unexpected TOK_TYPEDEF

line 59:

  typedef enum logic           {IDLE, WAIT} state_t;

so that would be information lost (iverilog supports the typedef keyword)

yosys> help read_verilog

    -sv
        enable support for SystemVerilog features. (only a small subset
        of SystemVerilog is supported)



yosys> read_verilog -sv load_unit.sv 
1. Executing Verilog-2005 frontend.
Parsing SystemVerilog input from `load_unit.sv' to AST representation.
load_unit.sv:22: ERROR: syntax error, unexpected TOK_ID, expecting ',' or '='
or ')'

(there's a type there):
    input  lsu_ctrl_t                lsu_ctrl_i,

if i put the import back in (which iverilog barfs on) yosys still barfs:
https://github.com/steveicarus/iverilog/issues/102

import ariane_pkg::*; // <<----

module load_unit (

this is a known issue in icarus verilog... and i can *guarantee* it will
be easier to fix that in the python-ply BNF than it will be to try to
patch the (c-based) iverilog source code, first.


so...

* yosys isn't up to the job and it would be months possibly years
  until any feature requested is added to support *Cadence* undocumented
  systemverilog features

* iverilog likewise would be months to add the same... and the developer
  would require to go in a different direction anyway

* yosys would destroy valuable information, performing hardware-suitable
  topological translations

* we need a language *translator* where yosys is a language *compiler*.

  a language translator's focus is to preserve as much of the original
  language's features (such as code comments, structure, order of
  the original code and so on)

* extracting the BNF syntax from iverilog is done already (automated)

* modifying the BNF syntax will be a heck of a lot easier without the
  primary purpose of either yosys or iverilog being in the way

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