[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> yosys> read_verilog fsm_expand.sv 
> 1. Executing Verilog-2005 frontend.
> Parsing Verilog input from `fsm_expand.sv' to AST representation.
> Lexer warning: The SystemVerilog keyword `logic' (at fsm_expand.sv:21) is
> not recognized unless read_verilog is called with -sv!
> fsm_expand.sv:21: ERROR: syntax error, unexpected TOK_ID, expecting ',' or
> '=' or ')'
did you try `read_verilog -sv fsm_expand.sv`?

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