[libre-riscv-dev] kestrel kcp53000 developer making a nmigen RISC-V core

[Luke Kenneth Casson Leighton]

On Wed, Apr 10, 2019 at 6:49 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> > https://github.com/KestrelComputer/polaris/blob/master/processor/rtl/SMG/seq.smg
> >
> neat

 thought you might like it :)

> >  the PLU-style FSM he based on studies of how the 6502 works.  i could
> > have the acronym wrong....
> >
> I think you meant PLA.

 yes! gah, took me 8 weeks to remember a girl's name, once. michelle.
that was 1990 and i still remember now. my memory's weird.

> just thought it would be really neat to write a program that's a processor
> compiler (like LLVM, but for digital logic) in that you feed in the
> definition of the ISA and the ALUs and it automatically generates a
> processor including all the pipelines, forwarding, stalling, and other
> logic.

 uh-huh.  i hear ya.

> I was halfway hoping that samuel's code would be that impressive.

 yyehhh it seems to make a full combinatorial block: i see no reason
why that combinatorial block should not then be used *in* a pipelined
design.

 hypothetically speaking: extending the syntax to be able to create
synchronisation-points.... mmm now it's beginning to turn more into a
programming language, and we know where that leads (php, zope/plone,
and when the syntax/pseudo-language fails, code-fragments in another
programming language are inserted into markup-style syntaxen....
*shudder*)

 at the very least, the SMA syntax - and the file that samuel
developed - is an extremely compact, clear and elegant way to take a
*massive* chunk of drudge work out of designing a RISC-V processor.

l.